Competing demands on integrated circuit manufacturers require them to reduce costs while maintaining the quality of their products. Consequently, manufacturers and designers have expended great effort in developing testing techniques to minimize the number of defective products shipped to customers. Such testing techniques include certain "pass/fail" tests on a sampling of semiconductor products prior to shipment to detect the presence of a defect in the products.
However, cost reduction also requires elimination of the causes of defects in order to improve manufacturing yield. Hence, semiconductor manufacturers must screen for defective parts, as well as identify the reasons and locations of defects in the defective parts so that appropriate changes can be made in the design and processing of the semiconductor products to reduce the incidence of such defects or faults.
The most common fault model used in the testing community is the "stuck-at" fault model. The stuck-at fault model assumes that a defect in an integrated circuit behaves like a node in the circuit that is stuck-at-1 or stuck-at-0. Although most of the possible defects in an integrated circuit can be modeled by using this fault model, there are some exceptions. One of the noted exceptions is the bridging fault, i.e., shorting between two signal lines in the physical layout.
To assertain a functional fault in an integrated circuit, electron beam probing is a powerful technique for analyzing the functional fault. A common approach used for isolating these defects is to back trace an incorrect signal on a failing pin through the circuit, by probing each node. The inputs and outputs of each logical node can be compared against simulated results to determine functionality. However, this method has several limitations. Most notably, this back-tracing method is often an extremely time consuming process. In order to reduce the time required for back-tracing defect isolation, scan-path design,s have been introduced which increase the observability and controllability of internal circuit nodes. The use of application specific integrated circuit (ASIC) scan-path architecture is increasing due to the improved testability compared to non-scan designs. Scan-path architecture also offers opportunities for more efficient failure analysis of functional faults.
Electron beam probing is based on the principle of "voltage-contrast imaging." A failing device is mounted in a vacuum chamber and an image is generated by raster scanning a beam of electrons over the surface of the device. When the beam impacts the surface of the device, secondary electrons are generated and can be detected. The detection mechanism produces a real-time image of the surface of the device on a computer monitor. Areas of the device which are at zero or low voltages appear lighter since more secondary electrons are generated. Those areas which are more positive in voltage appear darker since those areas emit fewer secondary electrons. An additional feature, analogous to a sampling oscilloscope, allows the user to acquire waveforms at selected points on the surface of the device.
To determine the failure location, the device is mounted on a tester which subjects the device to predetermined signals, referred to as test vectors or vectors. Certain signals or vectors will "pass" and certain signals or vectors will "fail," even in most faulty circuits. The test head is then docked with the electron beam prober. A loop of vectors, including the failing vector or vectors, is then established, and the electron beam prober is synchronized to the looping frequency of the tester. Beginning at a failing bond pad, waveforms are acquired using the electron beam prober and compared with simulated waveforms created from design of the device. Using this technique, an analyst backtraces through the logic, comparing the inputs and outputs of each cell with the simulation waveforms. Eventually, a cell will be located which has correctly functioning inputs and an incorrect output. Internal probing of the faulty cell and additional techniques including stroboscopic imaging are often sufficient to precisely locate the defect.
The use of multiple layers of metalization and ever-increasing circuit densities have introduced additional difficulty in the timely analysis of functional failures. Furthermore, failure analysts are often unfamiliar with the circuit design of an ASIC and may have limited access to design personnel to assist with the analysis.
With higher circuit densities and multi-layers of metalization, the backtracing method of locating defects using an electron beam prober has become increasingly difficult. The number of nodes which must be probed can be prohibitive-locating a faulty cell often requires the analyst to probe tens or hundreds of cells which is extremely time consuming. Multi-layer metalization requires additional sample preparation in order to probe lower levels. Although it is possible to probe conductors through the dielectric layers, the signal quality degrades with increasing dielectric thickness. To obtain better signals, portions of the dielectric layers are removed using a plasma or reactive ion etch. In certain cases; it is necessary to create probe points; however, this method can be time consuming if it is required at a large number of nodes.
Furthermore, simulation of waveforms using design software has become computer time intensive. For devices with high gate counts, it is not feasible to simulate all of the internal waveforms simultaneously. Instead, current procedures probe a small number of cells and simulate the relevant waveforms for comparison. This method is repeated--probing and simulating a small number of cells at a time--until the faulty cell is located.
These limitations with backtracing have led to increasingly lengthy cycle times, and have driven the need for a more efficient method for locating functional defects.
There also remains a need for a system and method for the isolation of defects in integrated circuits that combine the defect simulation on the tester, with subsequent beam probing, to reduce the number of nodes that must be probed. The system and method should further include a means of iteratively reducing the number of nodes for testing by repeating the scan-path testing, until a manageable number of nodes has been identified.